Which haswell

The key realisation behind TSX is that the processor already has hardware capable of arbitrating between conflicting memory accesses: that's what the cache mechanism does all the time. As a result, the cache system is pressed into service to provide two new ways to protect transactions in Haswell. If that fails because of other process activity, the processor rolls back the affected process to the state it was in before it started and transfers control to an abort sequence — which will probably try again with traditional locks.

The trouble with RTM is that it's Haswell-specific and won't run on any previous architectures. The other mechanism, Hardware Lock Elision HLE , is rather clever: it works in conjunction with standard locks in such a way that pre-Haswell processors will just ignore it and use their older locking mechanism. Haswell, however, will effectively ignore the lock instructions and let processes assume they've got a successful lock even if another process is in conflict.

If everything goes well because neither process writes new data to the protected memory, then all processes complete happily. If there is contention with writes to protected memory, the processor rolls back the affected process and returns it to a point where it set the lock — telling it the lock failed. Intel says it will be very simple for programmers to add these prefixes — ignored by pre-Haswell processors — to existing code, which will require no other changes.

Intel says that TSX will improve scalability in many database applications, seeing greater benefits from larger numbers of cores, while also reducing power-hungry memory accesses. Limitations imposed by the cache architecture constrain the memory areas that can be protected, but both conceptually and practically TSX seems like a useful addition to the parallel programmers' armoury.

Haswell's incremental improvements are a familiar cadence, with strong moves towards better system-on-chip products that have useful improvements in battery life, cost and form factors; other enhancements signal Intel's intention to fight fiercely in high-performance and graphic-intensive markets. There's no single big improvement, but for an architecture in late middle age to be capable of such feistiness on multiple fronts is commendable.

Image: Intel. More from TechRepublic Premium. BYOD: Managing and securing your mobile workforce. Checklist: Onboarding and offboarding C-level executives. For desktop and mobile, Haswell is branded as 4th Generation Intel Core processors. Haswell-based chips are manufactured on Intel's 22 nm process. While sharing a lot of similarities with its predecessor Ivy Bridge , Haswell introduces many new enhancements and features.

Haswell is the first desktop-line of x86s by Intel tailored for a system on chip architecture. This is a significant move that will continue to be developed over the next couple of microarchitectures.

Overall Haswell shares the same basic flow as Sandy Bridge and Ivy but expands on them considerably in the execution engine with wider execution units and additional scheduler ports. The memory hierarchy in Haswell had a number of changes from its predecessor. Significant enhancements have been done to support the new gather instructions and transactional memory.

With Haswell new port 7 which adds an address generation for stores, up to two loads and one store are possible each cycle. Additionally there is a unified second level TLB. The front-end is the complicated part of the microarchitecture as it deals with variable length x86 instructions ranging from 1 to 15 bytes.

The main goal here is to fetch and decode correctly the next set of instructions. The fetched instructions are then moved on to an instruction queue which has 40 entries, 20 for each thread.

Haswell continued to improve the branch misses although the exact details have not been made public. Nothing fundamentally changes with these refresh processors. It is the same design underneath. Now that Intel has been making Haswell wafers, the process is slightly more efficient over time ironing out production and the processor bins can all be shifted.

If Intel were to release new overclockable CPUs that were a simple speed bump but ultimately had no performance gain of the current overclocking CPUs, there might be a backlash. It will probably be the same silicon underneath as the iK due to the nature of the refresh, perhaps with a small design tweak that does not require new masks. We will review the new overclocking processor when we receive a sample from Intel, hopefully under something suitably extreme.

Back when Haswell was launched, we had only the chance to test the top line overclocking processor, the iK. This time around I was thankful to get the opportunity to expand our testing to the i5 and i3 segments of the processor line to find where they each stand in terms of performance. For comparison points we have the iK from our launch review, an iT from our ASRock M8 review , and an i we picked up along the way.

CPU benchmarking can be a bit of a nightmare in the current climate, especially on Intel platforms where turbo modes are possible. Where Intel might have a MHz base frequency and a MHz turbo frequency, a motherboard can detect that setting and override it for MHz on all cores by default. The upshot of this is in multi-threaded performance benchmarks, where due to the extra frequency the final result is higher than Intel specifications.

These CPU limitations are also felt in its mobile iterations. Intel quotes a per cent performance increase on Ivy Bridge processors clocked at the same speed, which is hardly earth shattering. That said we never found Ivy Bridge to be particularly slow. The other concerning aspect to Haswell is pricing. While Intel is keen to push down Ultrabook prices, it looks like higher end Ultrabooks are more likely to rise in price than fall. Ultimately, while Haswell does raise some issues, they fall by the wayside compared to the huge technical strides it makes.

In an ever more technologically mobile world battery life has been the a glaring shortcoming in our increasingly smart devices.

The fundamental problems with battery technology remain, but Haswell is a wonderful way to paper over its cracks. For everyone else, Haswell-based devices will start shipping during Q2 and with review models due with us shortly we fully expect a game changer. Editorial independence means being able to give an unbiased verdict about a product or company, with the avoidance of conflicts of interest.

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